COT Controlled Buck Converter

The effect of equivalent series resistance (ESR) of an output capacitor on the performance of a constant -on-time(COT)-controlled buck converter is studied and a pulse bursting phenomenon is revealed. It indicates that the ESR of the output capacitor is one of the key factors causing pulse bursting phenomenon in COT-controlled buck converters, and the critical ESR is derived via. It is pointed out that , when the ESR of the output capacitor is smaller than the critical ESR ,pulse bursting phenomenon occurs, otherwise it disappears. Simulation results are provided to verify the theoretical analysis results.

INTRODUCTION
The control techniques of switching dc-dc converters can be generally divided into the following three ways. 1) Constant –frequency control ,such as pulsewidth –modulation-based voltage-mode control and current- mode control 2) Variable-frequency control ,such as output-voltage-ripple-based control like constant-on-time (COT) control or constant-off-time control 3) Hybrid control

To improve the transient performance and to simplify the controller design of switching dc-dc converters, COT control has attracted much attention recently.COT control is simple to implement and easy to design, without an error amplifier and its corresponding compensation network.

In this paper , pulse bursting phenomenon of a COT-controlled buck converter is revealed via both time and s-domain analysis, the ESR of the output capacitor for the pulse bursting phenomenon is obtained. Simulation results are provided to verify the theoretical analysis.

PULSE BURSTING PHENOMENON
A) Review of COT Control

COT controller consisting of a comparator, an Reset-Set(RS) trigger, and an ON timer. From the wave forms, once the output voltage Vo decreases to the reference voltage Vref , the RS trigger will be triggered to turn on the power switch S to increase Vo, after the preset COT interval Ton , the RS trigger will be reset to turn off S, and it will be turned on again when Vo decreases to Vref to initiate the next switching period.

B) Pulse Bursting Phenomenon Analysis

At the end of the COT interval that is at the time instant when S is just turned off, Vo should be higher than Vref to maintain normal operation .Otherwise ,after a very short off time caused by the reset signal of RS trigger ,will follow consecutively until Vo increases to higher than Vref. In this case , pulse bursting phenomenon will occur, with large inductor current and output voltage ripples. The output voltage variation of a buck converter is composed of voltage variation across the output capacitor and its ESR resistor. The voltage variation across the ESR resistor is in proportion to the inductor current. That is the voltage across the ESR resistor will increase during the time interval when S is turned on, which helps to make the COT –controlled buck converter operate in normal operation. The voltage across the output capacitor may increase or decrease when S is turned on, depending on the relationship between the inductor current and load current. When the inductor current is lower than the load current , although S is on , the output capacitor will be discharged , which makes its voltage decrease. Thus when the output voltage variation is dominated by the output capacitor voltage variation, Vo may be lower than Vref during the time interval when S is turned on. In this case , normal operation cannot be ensured, and pulse bursting phenomenon will occur.

C) Critical ESR For Pulse Bursting Phenomenon
When the voltage VESR across the ESR resistor is large enough to dominate the output voltage variation , the COT-controlled buck converter operates normally without pulse bursting phenomenon. When VESR is not large enough to dominate the output voltage variation ,the pulse bursting phenomenon occurs . After some COT intervals ,S is turned off for a relatively long time , resulting in large inductor current and output voltage variation. Between the adjacent COT intervals there is a very short off time caused by the reset signals of the RS trigger. If the slope of – VESR is less than or equal to that of Vc_ripple at the time instant when S is just turned off, normal operation can be ensured, and no pulse bursting phenomenon occurs. Otherwise , the buck converter will operate abnormally and pulse bursting phenomenon will occur. The slopes of –VESR and Vc_ripple at the time instant when S is just turned on can be obtained as

d(-VESR)dt|t=nTs= -dRESRiL-Iodt|t=nTs
= -RESRVin-VoL
dVc_rippledt|t=nTs= iL-Io/C|t=nTs
= -∆IL2C
= -Vin-VoTON2LC
respectively , where ∆IL is the peak –to-peak value of the inductor current in steady state. Equating the above two equations , the critical ESR RESRC can be obtained as
RESRC= TON/2C
To ensure normal operation ,RESR must be greater than RESRC. Otherwise , the COT –controlled buck converter will work abnormally, and pulse bursting will occur. From the above equation ,we can further have

ℷ=RESR≥TON2
That is once TON is designed ,the time constant ℷ of the output capacitor must be designed to be greater than TON/2

COT controlled buck converter a) Circuit block diagram b) main operation wave forms

Waveforms under two cases a) with large RESRand b) with small RESR SIMULATION AND EXPERIMENTAL RESULTS

MATLAB/ SIMULINK MODEL for COT –Controlled Buck converter

Time-domain simulation results of the COT-controlled buck converter with RESR=5mΩ

Time-domain simulation results of the COT-controlled buck converter with RESR=2Ω

Variable| Signification| Value|
Vin| Input voltage| 15V|
VO| Output voltage| 5V|
L| Inductane| 66.7mH|
C| Capacitance| 2.498mF|
R| Load resistance| 5Ω|
Ton| Constant on-time| 6.67ms|

PARAMETERS OF THE COT- CONTROLLED BUCK CONVERTER

ANALYSIS AND DESIGN
Using Vin=15V and VO=5V
Vo =kVS ,From this equation k=1/3 ,ie TONT=1/3
Here T is taken as 20ms ,then TON=6.67ms
Using the formula, C=Vsk1-k8∆VcLf2 C=2.498Mf
L=Vsk1-k∆IfL=66.7mH
RESRC= TON/2C RESRC=1.33Ω

Here the simulation results are shown with RESR=5mΩ and 2Ω One of the equivalent resistance greater than critical value and the other is less than RESRC Limitation: Here the MATLAB/SIMULINK Model does not contain flip flop , comparator, reference voltage as shown in the circuit block diagram, because of the connection difficulties in MATLAB. So the pulse bursting is not completely visible in the simulated wave forms. Based on the reference paper the simulated waveform is

a) With 5mΩb) With 20mΩ
CONCLUSION
In this paper, a pulse bursting phenomenon ,which is a complex nonlinear phenomenon ,in a COT –controlled buck converter has been revealed . It is indicated that the ESR of the output capacitor has great effect on the control performance of the COT-controlled buck converter .The investigation results presented in this paper provide a useful guideline for the design of COT-controlled buck converters,eg: ceramic capacitors are usually not appropriate as output filter capacitor they have very small ESR.

REFERENCES
1] E.Figueres ,G.Garcera,J.M.Benavent,M.Pascual,and J.A.Martinez,”Adaptive two- loop voltage mode control of dc-dc switching converters,”IEEE Trans.Ind.Electron.,vol.53,no.1,pp.239-253,Feb.2006. 2]Y-S Lai and C-A Yeh,” Predictive digital- controlled converter with peak-current-mode control and leading edge modulation,” IEEE Trans.Ind.Electron.,vol.56,no.6,pp.1854-1863,jun 2009. 3]Analysis of pulse bursting phenomenon in COT controlled buck converter, IEEE Trans.Ind.Electron,vol58 ,No 12,.dec 2011