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Wireless led display board using GSM

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  • Category: Computers

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The scrolling message display will allow the user to type in any alphanumeric message and see it displayed through an array of red LED’s (Light Emitting Diodes). A block diagram illustrating this process is depicted.

This project will be an embedded system, so the display will be able to scroll messages anywhere there is a wall outlet. It will be dependent on a PC for user input. Messages can be created and saved on the display’s microcomputer by use of a terminal program on a PC. The PC and microcomputer  will communicate via serial port. After the message is created and saved, the display can be detached from the PC and then plugged in elsewhere to scroll the message. The array of LED’s will be configured together on a single board called a module.

The circuit board was designed with the microcontroller located on the back of the circuit board leaving just the display and reset button on the front. Your message is hard coded into code space within the microcontroller..

The Intel 8051 is Harvard architecture, single chip microcontroller (µC) which was developed by Intel in 1980 for use in embedded systems.
Intel’s original versions were popular in the 1980s and early 1990s, but has today largely been superseded by a vast range of faster and/or functionally enhanced 8051-compatible devices manufactured by more than 20 independent manufacturers including Atmel, Infineon Technologies (formerly Siemens AG), Maxim Integrated Products (via its Dallas Semiconductor subsidiary), NXP (formerly Philips Semiconductor), Nuvoton (formerly Winbond), ST Microelectronics, Silicon Laboratories (formerly Cygnal), Texas Instruments and Cypress Semiconductor.

PIC 16F72 Micro controller
PIC (Peripheral interface controller) is the IC while was eveloped to control the peripheral device, dispersing the function of the main CPU. PIC has the calculation function and the memory like the CPU and is controlled by the software. However the throughput, the memory capacity aren’t big. It depends on kind of PIC but the maximum operation clock frequency is about 20MHZ and the memory capacity to write the program is about 1K to 4K words. The clock frequency is related with the speed to read the program and to execute the instruction. Only at the clock frequency, the throughput cannot be judged. It changes with the architecture in the processing parts for same architecture; the one with the higher clock frequency is higher about the throughput. The point, which the PIC convenient for is that the calculation part, the memory, the input/output part and soon, are incorporated into one piece of the IC. The efficiency, the function is limited but can compose the control unit only by the PIC even if it doesn’t combine the various IC’s so, the circuit can be compactly made .

The PIC16F72 belongs to the Mid-Range family of the PIC devices. Core architecture
The PIC architecture is distinctively minimalist. It is characterized by the following features: ď‚·


A single accumulator (W), the use of which (as source operand) is implied (i.e. is not encoded in the opcode)
All RAM locations function as registers as both source and/or destination of math and other functions. A hardware stack for storing return addresses
A fairly small amount of addressable data space (typically 256 bytes), extended through banking Data space mapped CPU, port, and peripheral registers
The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).

Unlike most other CPUs, there is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers. Data space (RAM)

PICs have a set of registers that function as general purpose RAM. Special purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend the addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices (i.e., the baseline and mid-range cores), any register move had to be achieved via the accumulator.

To implement indirect addressing, a “file select register” (FSR) and “indirect register” (INDF) are used: A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP). External data memory is not directly addressable except in some high pin count PIC18 devices. Code space

All PICs feature Harvard architecture, so the code space and the data space are separate. PIC code space is generally implemented as EPROM, ROM, or flash ROM. In general, external code memory is not directly addressable due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices. Word size

The word size of PICs can be a source of confusion. All PICs handle (and address) data in 8-bit chunks, so they should be called 8-bit microcontrollers. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline and midrange families have program memory addressable in the same wordsize as the instruction width, ie. www.BEProjectReport.com

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12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits. In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.

PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices. Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high level language compilers.

Instruction set
A PIC’s instructions vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching. Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W; writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the “high end” cores.

PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are: ‘skip if bit set’, and, ‘skip if bit not set’. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction.

The PIC architecture has no (or very meager) hardware support for automatically saving processor state when servicing interrupts. The 18 series improved this situation by implementing shadow registers which save several important registers during an interrupt. In general, PIC instructions fall into 5 classes:

1. Operation on W with 8-bit immediate (“literal”) operand. E.g. movlw (move literal to W), andlw (AND literal with W). One instruction peculiar to the PIC is retlw, load immediate into W and return, which is used with computed branches to produce lookup tables. www.BEProjectReport.com

2. Operation with W and indexed register. The result can be written to either the W register (e.g. addwf reg,w). or the selected register (e.g. addwf reg,f).
3. Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as “branch on carry clear” are possible.

4. Control transfers. Other than the skip instructions previously mentioned, there are only two: goto and call.
5. A few miscellaneous zero-operand instructions, such as return from subroutine, and sleep to enter low-power mode.
Many of these architectural decisions are directed at the maximization of top-end speed, or more precisely of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs, and is still among the simplest and cheapest. The Harvard architecture—in which instructions and data come from conveniently separate sources—simplifies timing and microcircuit design greatly, and this pays benefits in areas like clock speed, price, and power consumption. The PIC is particularly suited to implementation of fast lookup tables in the program space. Such lookups are O(1) and can complete via a single instruction taking two instruction cycles. Basically any function can be modelled in this way. Such optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 x 14-bit words on the 16F690) and by the design of the instruction set, which allows for embedded constants.

The simplicity of the PIC, and its scalar nature, also serve to greatly simplify the construction of real-time code. It is typically possible to multiply the line count of a PIC assembler listing by the instruction cycle time to determine execution time. (This is true because skip-based instructions take 2 cycles whether the skip occurs or doesn’t.) On other CPUs (even the Atmel, with its MUL instruction), such quick methods are just not possible. In low-level development, precise timing is often critical to the success of the application, and the real-time features of the PIC can save crucial engineering time.

A similarly useful and unique property of PICs is that their interrupt latency is constant (it’s also low: 3 instruction cycles). The delay is constant even though instructions can take one or two instruction cycles: a dead cycle is optionally inserted into the interrupt response sequence to make this true. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. Other microcontrollers can do this in some cases, but it’s awkward. The non-interrupt code has to anticipate the interrupt and enter into a sleep state before it arrives. On PICs, there is no need for this.

The three-cycle latency is increased in practice because the PIC does not store its registers when entering the interrupt routine. Typically, 4 instructions are needed to store the W-register, the status register and switch to a specific bank before starting the actual interrupt processing. Limitations

The PIC architectures have several limitations:

Only a single accumulator
A small instruction set
Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator Memory must be directly referenced in arithmetic and logic operations, although indirect addressing is available via 2 additional registers

Conditional skip instructions are used instead of conditional jump instructions used by most other architectures
Indexed addressing mode is very rudimentary
o The hardware call stack is so small that program structure must often be
flattened o The hardware call stack is not addressable, so pre-emptive task switching cannot be implemented
o Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables
Program memory is not directly addressable, and thus space-inefficient and/or timeconsuming to access. (This is true of most Harvard architecture microcontrollers.)

With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler. Compiler development

These properties have made it difficult to develop compilers that target PIC microcontrollers. While several commercial compilers are available, in 2008, Microchip finally released their C compilers, C18, and C30 for their line of 18f 24f and 30/33f processors. By contrast, Atmel’s AVR microcontrollers—which are competitive with PIC in terms of hardware capabilities and price, but feature a RISC instruction set—have long been supported by the GNU C Compiler. www.BEProjectReport.com


Also, because of these properties, PIC assembly language code can be difficult to comprehend. Judicious use of simple macros can make PIC assembly language much more palatable, but at the cost of a reduction in performance. For example, the original Parallax PIC assembler (“SPASM”) has macros which hide W and make the PIC look like a two-address machine. It has macro instructions like “mov b,a” (move the data from address a to address
b) and “add b,a” (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as “cjne a,b,dest” (compare a with b and jump to dest if they are not equal).

Baseline Core devices
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.

Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.

The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking. CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the staus register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page. The instruction set is as follows. Register numbers are referred to as “f”, while constants are referred to as “k”. Bit numbers (0–7) are selected by “b”. The “d” bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. 12-bit PIC instruction set

Mid-Range core devices
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the increased opcode width allows 128 registers and 2048 words of code to be directly addressed. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

The first 32 bytes of the register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16 registers (0x70–0x7F) are global, as are a few of the most important special-purpose registers, including the STATUS register which holds the RAM bank select bits. (The other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high preload register PCLATH, and the master interrupt control register INTCON.)

The PCLATH register supplies high-order instruction address bits when the 8 bits supplied by a write to the PCL register, or the 11 bits supplied by a GOTO or CALL instruction, is not sufficient to address the available ROM space.
The 17 series never became popular and has been superseded by the PIC18 architecture. It is not recommended for new designs, and availability may be limited. Improvements over earlier cores are 16-bit wide opcodes (allowing many new instructions), and a 16 level deep call stack. PIC17 devices were produced in packages from 40 to 68 pins. The 17 series introduced a number of important new features: ď‚·


PIC18 High End core devices
Microchip introduced the PIC18 architecture in 2000. Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.

The auto increment/decrement feature was improved by removing the control bits and adding four new indirect registers per FSR. Depending on which indirect file register is being accessed it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR.

In more advanced PIC18 devices, an “extended mode” is available which makes the addressing even more favorable to compiled code:

a new offset addressing mode; some addresses which were relative to the access bank are now interpreted relative to the FSR2 register the addition of several new instructions, notable for manipulating the FSR registers.

These changes were primarily aimed at improving the efficiency of a data stack implementation. If FSR2 is used either as the stack pointer or frame pointer, stack items may be easily indexed— allowing more efficient re-entrant code. Microchip C18 chooses to use FSR2 as a frame pointer. PIC24 and dsPIC 16-bit microcontrollers

In 2001, Microchip introduced the dsPIC series of chips, which entered mass production in late 2004. They are Microchip’s first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition. Architecturally, although they share the PIC moniker, they are very different from the 8-bit PICs. The most notable differences are:

they feature a set of 16 working registers (W0-W15)
they fully support a stack in RAM, and do not have a hardware stack bank switching is not required to access RAM or special function registers data stored in program memory can be accessed directly using a feature called Program Space Visibility

The first generation of PICs with EPROM storage are almost completely replaced by chips with Flash memory. Likewise, the original 12-bit instruction set of the PIC1650 and its direct descendants has been superseded by 14-bit and 16-bit instruction sets. Microchip still sells OTP (one-timeprogrammable) and windowed (UV-erasable) versions of some of its EPROM based PICs for legacy support or volume orders. It should be noted that the Microchip website lists PICs that are not electrically erasable as OTP despite the fact that UV erasable windowed versions of these chips can be ordered.

The original PIC was built to be used with General Instruments’ new 16-bit CPU, the CP1600. While generally a good CPU, the CP1600 had poor I/O performance, and the 8-bit PIC was developed in 1975 to improve performance of the overall system by offloading I/O tasks from the CPU. The PIC used simple microcode stored in ROM to perform its tasks, and although the term wasn’t used at the time, it shares some common features with RISC designs.

In 1985 General Instruments spun off their microelectronics division, and the new ownership canceled almost everything — which by this time was mostly out-of-date. The PIC, however, was upgraded with internal EPROM to produce a programmable channel controller, and today a huge variety of PICs are available with various on-board peripherals (serial communication modules,
UARTs, motor control kernels, etc.) and program memory from 256 words to 64k words and more (a “word” is one assembly language instruction, varying from 12, 14 or 16 bits depending on the specific PIC micro family).

PIC and PICmicro are registered trademarks of Microchip Technology. It is generally thought that PIC stands for Peripheral Interface Controller, although General Instruments’ original acronym for the initial PIC1640 and PIC1650 devices was “Programmable Interface Controller”. The acronym was quickly replaced with “Programmable Intelligent Computer”

The Microchip 16C84 (PIC16x84), introduced in 1993,was the first CPU with on-chip EEPROM memory. This electrically-erasable memory made it cost less than CPUs that required a quartz “erase window” for erasing EPROM.

Device Programmers

Devices called “programmers” are traditionally used to get program code into the target PIC. Most PICs that Microchip currently sell feature ICSP (In Circuit Serial Programming) and/or LVP (Low Voltage Programming) capabilities, allowing the PIC to be programmed while it is sitting in the target circuit. ICSP programming is performed using two pins, clock and data, while a high voltage (12V) is present on the Vpp/MCLR pin. Low voltage programming dispenses with the high voltage, but reserves exclusive use of an I/O pin and can therefore be disabled to recover the pin for other uses (once disabled it can only be re-enabled using high voltage programming). There are many programmers for PIC microcontrollers, ranging from the extremely simple designs which rely on ICSP to allow direct download of code from a host computer, to intelligent programmers that can verify the device at several supply voltages. Many of these complex programmers use a pre-programmed PIC themselves to send the programming commands to the PIC that is to be programmed. The intelligent type of programmer is needed to program earlier PIC models (mostly EPROM type) which do not support in-circuit programming. Many of the higher end flash based PICs can also self-program (write to their own program memory). Demo boards are available with a small bootloader factory programmed that can be used to load user programs over an interface such as RS-232 or USB, thus obviating the need for a programmer device. Alternatively there is bootloader firmware available that the user can load onto the PIC using ICSP. The advantages of a bootloader over ICSP is the far superior programming speeds, immediate program execution following programming, and the ability to both debug and program using the same cable.

Microchip Programmers

Microchip PICSTART Plus programmer
There are many programmers/debuggers available directly from Microchip. Current Microchip Programmers (as of 1/2010)


Third-Party Programmers
There are programmers available from other sources, ranging from plans to build your own, to selfassembly kits and fully tested ready-to-go units. Some are simple designs which require a PC to do the low-level programming signalling (these typically connect to the serial or parallel port and consist of a few simple components), while others have the programming logic built into them (these typically use a serial or USB connection, are usually faster, and are often built using PICs themselves for control). For a directory of PIC related tools and websites, see PIC microcontroller at the Open Directory Project.

These are some common programmer types:

Simple serial port ICSP programmers
o These generally rely on driving the PIC’s Vss line negative to get the
necessary voltage differences from programming. Hence they are compact and cheap but great care is needed if using them for in circuit programming.

Simple parallel port ICSP programmers
o Simple to understand but often have much higher part counts and generally require external power supplies.
Intelligent programmers (some use USB port)
o Generally faster and more reliable (especially on laptops which tend to have idiosyncrasies in the way they implement their ports) but far more complex to build (in particular they tend to use a PIC in the programmer which must itself be programmed somehow).

High Performance RISC CPU
• Only

35 single word instructions to learn
• All single cycle instructions except for program branches, which are two-cycle • Operating speed: DC – 20 MHz clock input
DC – 200 ns instruction cycle
• 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM) • Pinout compatible to PIC16C72/72A and PIC16F872
• Interrupt capability
• Eight-level deep hardware stack
• Direct, Indirect and Relative Addressing modes

Peripheral Features:
• High

Sink/Source Current: 25 mA
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture, Compare, PWM (CCP) module
– Capture is 16-bit, max. resolution is 12.5 ns

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– Compare is 16-bit, max. resolution is 200 ns
– PWM max. resolution is 10-bit
• 8-bit, 5-channel analog-to-digital converter
• Synchronous Serial Port (SSP) with SPI™ (Master/Slave) and I2C™ (Slave) • Brown-out detection circuitry for Brown-out Reset (BOR)
CMOS Technology:

• Low power, high speed CMOS FLASH technology
• Fully static design
• Wide operating voltage range: 2.0V to 5.5V
• Industrial temperature range
• Low power consumption:
– < 0.6 mA typical @ 3V, 4 MHz
– 20 ÎĽA typical @ 3V, 32 kHz
– < 1 ÎĽA typical standby current

There are two memory blocks in the PIC16F72 device. These are the program memory and the data memory. Each block has separate buses so that concurrent access can occur. Program memory and data memory are explained in this section. Program memory can be read internally by the user code The data
memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the ―core‖ are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module.

PIC16F72 devices have a 13-bit program counter capable of addressing a 8K x 14 program memory space. The address range for this program memory is 0000h – 07FFh. Accessing a location above the physically implemented address will cause a wraparound.

The RESET Vector is at 0000h and the Interrupt Vector is at 0004h.

The Data Memory is partitioned into multiple banks that contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS) and RP0 (STATUS) are the bank select bits. Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain SFRs. Some ―high use‖ SFRs from one bank may be mirrored in another bank, for code reduction and quicker access (e.g., the STATUS register is in Banks 0 – 3).

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA
bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register, reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.

Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB
bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).

PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each www.BEProjectReport.com

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PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, readmodifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided.

The FLASH Program Memory is readable during normal operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR). Up to 14-bit wide numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP. There are five SFRs used to read the program and memory:

The program memory allows word reads. Program memory access allows for checksum calculation and reading calibration tables.

These devices have a host of features intended to maximize system
reliability, minimize cost through elimination of external components, provide power saving

Operating modes and offer code protection:
• Oscillator Selection
– Power-on Reset (POR)
– Power-up Timer (PWRT)
– Oscillator Start-up Timer (OST)
– Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Code Protection
• ID Locations
• In-Circuit Serial Programming

These devices have a Watchdog Timer, which can be enabled or disabled using a configuration bit. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes, and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. Configuration bits are used to select the desired oscillator mode.

1. Micro controller
2. MCU Clock
3. Display Column selection
4. Display Row selection
5. Data communication
6. EEPROM interfacing
7. Program button interfacing
8. Power supply
10. 7X5 Dot Matrix Of 7 Character Long Board

1] Micro controller
PIC 16F72 is the heart of the circuit which calls all of the shots. In normal operation when the display is scrolling a message its task is to read data from the EEPROM, clock out a pulse to the column selector IC’s, which drive the columns, then spit out data at the rows. This is all done very,very fast as you would imagine. A 20MHz crystal and associated 22pf caps provide a clock sourcefor the micro. All of the magic is in the software. The bulk of the hardware is configured as a ―workhorse‖ if you like. It’s a no brainier. During programming of the message into the display via the Windows based software, the micros main role is to read the serial data and organize it into the EEPROM.

Programming the message involves pressing the program button of the unit so that the PIC micro is ready to receive serial data from the Windows based software. This data is then transferred into a serial 24C256, 256Kb EEPROM for later recall. After successful programming the display will scroll from right to left the message that you just programmed in. The scroll speed can be ―tweaked‖ via the Windows based software and you can set the number of times the message repeats. In data terms, what’s actually stored on the EEPROM is the row data that is broken down from the characters that you program.
The characters are all upper case, In normal operation the PIC just scans through this data in the EEPROM and outputs it at the rows and provides a clock source that increment 5 column counters that are connected to the columns. It’s just a common multiplexing arrangement procedure,


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2] MCU Clock
Clock signal for the micro controller provided by crystal Y1 (20MHZ) the two 22PF capacitors hanging off it ensure correct loading for the crystal, so that it starts reliably.

3] Display Column selection
In essence a column selector IC receives clock pulses at its clock pin and in turn increments one of its output lines (Q0 – Q7) sequentially. When first powered up Q0 will be set high. As soon as the first clock pulse arrives Q0 will go low and Q1 will go high. At the arrival of the next pulse Q1 will swing low and Q2 will go high. There are only eight outputs on this IC so by itself it can’t possible be used to drive the required 35 columns. The solution is what’s called a cascaded arrangement. All ofthe column selector IC’s outputs are buffered via ULN2803 – driver IC.

4] Display Row selection
The PIC directly controls the rows via emitter follower buffers (Q1 – Q7). These are also driven well and truly into saturation by their respective 4K7 base resistors. 22E resistors limit the peak current to the LEDS.


5] Data communication
RC3 on the micro is the RX line designated to receive the serial data from the PC, because we are only using the RX line on the serial port to program in the message. These communicate with PC serial (RS232) port via current limiting resistor (R20). LED L2 provides data receiver indication and is driven by port RC1 via a 220E resistor. the excellent IO capabilities of the PIC micro controller range of devices, and the adoption of TTL levels on most modern PC serial ports, a line driver is often unnecessary unless long distances are involved between the transmitter and the receiver. Instead a simple current limiting resistor is all that’s required

6] EEPROM interfacing
RA0 & RA1 connect to the clock & data lines of IC9, serial EEPROM. This is a 256Kb device which operates serially at up to 600KHz!. The two 4K7 pull ups are essential since the data & clock lines are bipolar.

7] Program button interfacing

Programming the message involves pressing the program button of the unit so that the PIC micro is ready to receive serial data from the Windows based software. Port RC3 is pulled up via 10K resistor and used for programming message.

8] Power Supply
It’s based on 3 terminal voltage regulators, which provide the required +5V.Power is derived initially from standard 12V AC/DC adapter or 12V_500ma Transformer. This is fed to bridge rectifier D2 – D8, the output of which is then filtered using 1000uf electrolytic capacitor and fed to U3 (voltage regulator). U3 +5V output powers the PIC micro controller and other logic circuitry. LED L1 and its associate 1K current limiting resistors provide power indication. The unregulated voltage of approximately 12 V is required for matrix display driving circuit.


The AT24C256 are 256K bit electrically erasable programmable memories (EEPROM), They are manufactured in SGS-THOMSON’s Hi-Endurance Advanced CMOS technology, which guarantees an endurance of one million erase/write cycles with a data retention of 40 years. The memories operate with a power supply value as low as 1.8V for the ST24Cxxx The memories are compatible with the I2C standard, two wire serial interface which uses a bi-directional data bus and serial clock.

The memories carry a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. This issued together with 2 chip enable inputs (E2, E1) so that up to 4 x 4K devices may be attached to the I2C bus and selected individually. The memories behave as a slave device in the I2C protocol with all memory operations synchronized by the serial clock.

Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by a stream of 7 bits (identification code 1010), plus one read/write bit and terminated by an acknowledge bit.

This is used to make the stable voltage of +5V for U2 (MCU). The LM7805 is three terminal positive regulators are available in the TO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internal current limiting, thermal shut down and safe operating area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators,

Use the component overlay on the PCB to place the components starting with the lowest height components first. Make sure that the diode, LED and electrolytic capacitors are inserted the right way around.

1. Resistors and diodes
2. IC sockets
3. LED s
4. Ceramic capacitors. And crystal
5. Transistors (Q1 ~ Q7)

If we just made a big array of LED’s and controlled each one separately then we’d need a chip with about 200 pins for this small sign, and hundreds or thousands more for a larger sign. By using a few handy control and power techniques we’ve managed to build a scrolling LED sign with a lot of functionality in a small package and everything runs on a very simple 8-bit microcontroller.

So how do we control 192 pixels with a 28 pin microcontroller? A process called Multiplexing…it’s a lot like how you’re TV or computer screen works. Instead of trying to control each pixel all the time we scan through them much faster than the eye can see. Take a look at the schematic – you can see how all of the LED’s are connected. An individual LED has a cathode (negative) and anode (positive) lead. To make it light we just give it power and current flows from anode to cathode. Every LED in a given row has a common anode (most of these connections are made inside the LED matrix) and they’re connected to a transistor to VCC. The microcontroller can turn on any of the 8 row transistors and provide that row with a path to VCC (+V). Ok, now what about the cathode/negative terminal? On any given column all of the cathode are common and connect to the output pins of column selector IC (shift registers). That pin can either be low/0/negative in which case it will not supply current to flow through the LED, or it can be high/1/positive.

Why use shift registers here, can’t we just connect directly to the microcontroller? There are two good reasons why it’s designed this way and one has to do with power .The other is that it’s difficult/expensive to find a microcontroller with enough output pins. We would need 35 output pins just to control all the columns, but in this setup we just use 2 pins to provide clock and data to the shift registers. Also, this setup is infinitely expandable – just daisy chain more shift registers together to make a longer display. .

L.E.D. (Light Emitting Doide) are very exciting & excellent media for indoor & outdoor advertising and are clearly visible from very long distance. Character matrix display panels are cheaper to build than graphic matrix panels because fewer LEDs are used.

The smallest LED array built with 5×7 matrix blocks that also fits a block built with 8×8 matrix blocks is 8X34 pixels.This is called a matrix sub-block. Figure shows the matrix sub-block as landscape format, which is the common orientation. The matrix sub-block rotated into portrait format instead.

Display size: 8×34 pixels, (26.5.cm) x (5.5.cm)

The size of the target graphic panel should be an exact multiple of this matrix sub-block. If that can be achieved, the design will use the minimum number of drivers, and the software driver can treat the display as an orthogonal array of these matrix sub-blocks.


LED display circuit is interfaced to computer using serial port RS232. Now we install the setup in computers and after installation open the page and we change the speed settings and enter the word we want to display.

As we control the display board using computer , this project is called ―PC INTERFACED LED DOT MATRIX DISPLAY‖

This is the software setup page where we type the required word. For example we have just typed ― THANKFUL TO DR K.ALICE MARY, EEE HOD. And now we get the display in the dot matrix board.

For protecting the control board and the display board we can use playwood
and make a box and fit the circuit into it. Also if we cover the display board using red filter we get much glow compared to the normal one.

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