Inductive Reactance

Recorded Data:

Analysis and Conclusion

From the first plot, we see that the computed value for L is pretty consistent except in the very first case where the frequency was equal to 50Hz. We treat this case as an outlier and there is sufficient case to do so. At such a low frequency, there is the possibility that the reactance estimate for the inductor will not be accurate as the capacitive reactance would play a part. Even if the inherent capacitance in the inductor is low, at low frequencies, capacitive reactance dominates inductive reactance and as such, the estimate for the value of our inductor is not that accurate. If we take the average of the estimates for L except the case where F = 50, we get an average computed estimate for L of 0.244262 Henrys.

In the 2^nd plot, we see the relationship between the computed reactance and the frequency. It is clear that the reactance increases as the frequency is increased. The trendline on top of the plot was generated by Excel. The trendline was generated as a linear regression estimate with a forced y – intercept of zero since we know that at zero frequency, the reactance is zero. A linear regression model was chosen since the formula for reactance – X = 2πLF = is linear with respect to frequency. The trendline gives an estimate of y = 1.468x and a relatively high r² level of 0.95. The high r² indicates high correlation between the trendline and the data. If we take our L value to be equal to 0.244262 – our computed average, our computed reactance formula would be the following:

The trendline value, 1.468, is only 4% off from our computed reactance formula based on the average value of L. This indicates that the results of the experiment seem to verify the theoretical framework of inductive reactance and complex impedance.

Phasor Diagram

Since we will be drawing voltage referenced to current, then we will show the source voltage as leading since in inductive loads the current lags the voltage.  Next we draw the voltage drop across the resistor. Since the resistor has no reactive component, this voltage is parallel to the reference current.

Lastly, we draw the voltage drop across the inductor. From Kirchoff’s voltage law, we know that this phasor should return to the origin. The combined voltage drop of the resistor and inductor is equal to the source voltage.

Recorded Data:

Analysis and Conclusion

From the table, we see that a capacitance of 4.5uF makes the system draw the least amount of current from the power supply.

Drawing the phasor diagram

We know that the impedance of the lamp does not change since the only thing we are varying is the value of the capacitor. Given this and the fact that the lamp is connected in parallel with the supply voltage, then the phasor current across the lamp remains constant across all situations – a fact which is supported by our data. We see in the data that the magnitude of the lamp current more or less stays the same across all situations. Given that the lamp is an inductive load, we draw the lamp current as lagging the reference voltage. The angle at this point is arbitrary as well as the magnitude. This diagram only aims to show the relationship and scale was not taken into consideration.

Next, we draw the phasors for the source current. We know the magnitude of these currents and from the power factor, we know there relative angle from the source reference voltage, this allows us to draw approximately the source currents on our phasor diagram.

Finally, to complete the diagram, we draw the phasors of our capacitor currents.

From this method and from our data, we note several things:

1. Even with zero capacitance, there is a capacitor current reading. This means that there is still some impedance in the circuit – i.e. the circuit was not totally open. This is supported by the fact that at zero capacitance, the supply current and lamp current were not equal – a situation we would expect should the circuit have reduced into a single loop.
2. The capacitive currents are not purely reactive. The capacitor currents are also complex, this could arise from the presence of parasitic resistance in the capacitor path. This means that if we represent them as phasors, our capacitor currents would not be perfectly vertical.

Mathematically, we could show this. If our capacitor currents were perfectly reactive, then the real part of the supply current would be the same for each and every iteration since the capacitor would not contribute any real resistance. However, as the table below shows, this is not the case.

3.  From the above table, we also note an interesting relationship. At the optimum capacitance value, not only does the supply current magnitude goes to a minimum, the real component also drops to a minimum. This could be due to the lower copper losses coming from the lower current magnitude. These copper losses are purely resistive and as such would consume real current, not apparent or reactive current.

References

Hayt, W., Kemmerly, J., & Durbin, S. (2007). Engineering Circuit Analysis 7^th edition. New York: McGraw Hill

Gottlieb, I.M. (1994), Electric Motors & Control Techniques, 2nd Edition, TAB Books